A digital circuit has a tendency to decrease its power supply voltage for the requirements of higher speed and lower consumed power. The power supply voltage thereof has been changing from a 5V system to a 3.3V system and further to a lower voltage system. An error of ±10% is allowed for a power supply voltage of 3.3V, therefore a digital circuit should be guaranteed to be operated at 3.0V.
As an example of a digital circuit, a light-emitting element array may be considered. The light-emitting element array in which a number of light-emitting elements are integrated in the same substrate is used for a writing light-source of an optical printer head and the like in conjunction with its driver IC (Integrated Circuit).
The inventor of the present application has interested in a three-terminal light-emitting thyristor having a PNPN-structure as a component of a light-emitting element array, and has already proposed a self-scanning light-emitting element array for realizing a self-scanning function of light-emitting points (see Japanese Patent Publications Nos. 1-238962, 2-14584, 2-92650, and 2-92651). These patent publications have disclosed that self-scanning light-emitting arrays may be easily mounted for a writing light-source of an optical printer, the array pitch of light-emitting elements may be fined, a compact self-scanning light-emitting element array may be fabricated, and so on.
The inventor has also proposed a self-scanning light-emitting element array in which a switch element (a light-emitting thyristor) array is structured as a shift portion and is separated from a light-emitting element (a light-emitting thyristor) array structured as a light-emitting portion (see Japanese Patent Publication No. 2-263668). These proposed self-scanning light-emitting element array is structured so as to be operated by a driver IC of a 5V power supply system.
A power supply voltage for a driver IC has been changed from a 5V system to a 3.3V system as described above, because the consumed power therein may be reduced by decreasing a power supply voltage. Consequently, the light-emitting thyristor described above is also desirable to be operated by a 3.3V power supply system.
Referring to FIG. 1, there is shown an equivalent circuit diagram of a diode-coupled self-scanning light-emitting array driven by a voltage of 5V, in which a shift portion and light-emitting portion are separated. The self-scanning light-emitting element array comprises switches T1, T2, T3 . . . and write light-emitting element L1, L2, L3 . . . . Three-terminal light-emitting thyristors are used for both of the switch elements and write light-emitting elements. A diode-coupling structure is used in the shift portion, i.e., gates electrodes between adjacent switch elements are coupled together by a diode D, respectively. In the figure, VGA designates a power supply (normally −5V) which is connected to a gate electrode of each switch element via a load resistor. The gate electrode of each switch element is also connected to a gate electrode of a corresponding write light-emitting element. A start pulse φS is supplied to a gate electrode of the switch element T1, transfer clock pulses φ1 and φ2 alternately to cathode electrodes of the switch elements, and a write signal φI to cathode electrodes of the write light-emitting elements.
Referring to FIG. 2, there is shown a device structure of the self-scanning light-emitting element array in FIG. 1 formed in a chip, in which FIG. 2A is a plan view and FIG. 2B is a cross-sectional view taken along X-X line in FIG. 2A. As shown in the figures, on a P-type GaAs substrate 10 successively stacked are a P-type AlGaAs epitaxial layer 11, an N-type AlGaAs epitaxial layer 12, a P-type AlGaAs epitaxial layer 13, and an N-type AlGaAs epitaxial layer 14 to form a PNPN-structure. A self-scanning light-emitting element array is fabricated by using the PNPN-structure. Reference numeral 21 designates an ohmic electrode for the P-type AlGaAs layer 13, 22 an ohmic electrode for the N-type AlGaAs layer 14, 23 an ohmic electrode (a bottom common electrode) for the P-type GaAs layer 10, 60 a protective layer, 70 a VGA wiring, 71 a φ1 wiring, 72 a φ2 wiring, 73 a φI wiring, 80 a cathode island of the shift portion, 81 a cathode island for the coupling diode D, 82 a cathode island of the light-emitting portion, and 90 a resistor, respectively. In this structure, the coupling diode D uses upper two layers of the PNPN-structure, i.e., a P-N junction formed by the P-type AlGaAs layer 13 and N-type AlGaAs layer 14. The resistor 90 utilizes the P-type AlGaAs layer 13.
The operation of this self-scanning light-emitting array will now be described briefly. Assume that when transfer clock φ2 is driven to Low-level, the switch element T2 is turned on. At this time, the voltage of the gate electrode of the switch element T2 is elevated from −5V to approximately 0V. The effect of this voltage elevation is transferred to the gate electrode of the switch element T3 via the diode D to set the voltage thereof to approximately −1V which is a forward rise voltage (equal to a diffusion potential) of the diode D. However, the diode D is reverse-biased so that the voltage is not conducted to the gate G1, then the voltage of the gate electrode G1 remains at −5V. The turn-on voltage of a light-emitting thyristor is approximated to a gate electrode potential+a diffusion potential of a PN junction (approximately 1V) between a gate and cathode. Therefore, if a High-level voltage of a next transfer clock pulse φ2 is set to a voltage lower than approximately −2V (the voltage required to turn on the transfer element T3) and larger than approximately −4V (the voltage required to turn on the switch element T5), then only the switch element T3 is turned on and other switch elements remain off-state, respectively. As a result of which, on-state is transferred by means of the two-phase transfer clock pulses.
The start pulse φS works for starting the transfer operation described above. When the start pulse 0 is driven to High level (approximately OV) and the transfer clock pulse φ2 is driven to Low-level (approximately −2V-approximately −4V) at the same time, the transfer element T1 is turned on. Just after that, the start pulse φS is returned to a low level.
Assuming that the switch element T2 is in on-state, the voltage of the gate electrode of the switch element T2 is elevated from VGA to approximately 0V. Consequently, if the voltage of the write signal φI is lower than the diffusion potential (approximately 1V) of the PN junction, the light-emitting element L2 may be turned into a light-emitting state.
On the other hand, the voltage of the gate electrode of the switch element T1 is approximately −5V, and the voltage of the gate electrode of the switch element T3 is approximately −1V. Consequently, the write voltage of the light-emitting element L1 is approximately −6V, and the write voltage of the light-emitting element L3 is approximately −2V. It is appreciated that the voltage of the write signal φI which can write into only the light-emitting element L2 is in a range of (−1V)-(−2V). When the light-emitting element L2 is turned on, that is, in a light-emitting state, the amount of emitted light is determined by the amount of a current supplied by the write signal φI. Accordingly, the light-emitting elements may emit light at any desired amount thereof. In order to transfer on-state to the next light-emitting element, it is necessary to first turn off the element in on-state by temporarily dropping the voltage of the write signal φI down to 0V.
An operable voltage (a Low-level voltage of a clock pulse) VL for the diode-coupled self-scanning light-emitting element array described above is in the following condition;VL<VGON−2VD−Ith×RP wherein VGON is a gate voltage of a turned-on thyristor, VD a forward rise voltage of the coupling diode D, Ith a threshold current which turns on a thyristor, RP a parasitic resistor of a thyristor gate. VGON is approximately −0.3V, VD is 1.3v, and Ith×RP is approximately 0.3V, then VL is smaller than −3.1V. In order to realize a stable operation of the self-scanning light-emitting element array, an allowance of approximately 0.2V is required for the voltage VL. Consequently, a voltage of approximately 3.3V is required to operate the current self-scanning light-emitting element array. A 3.0V power supply system, therefore, can not operate the current self-scanning light-emitting element array.
While the PNPN-structure in which the P-type layer, N-type layer, P-type layer and N-type layer are stacked in this order on the P-type substrate has been illustrated, the PNPN-structure in which the N-type layer, P-type layer, N-type layer and P-type layer are stacked in this order on the N-type substrate may also be used, which has an opposite polarity in FIG. 1.